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general description the max8520/max8521 are designed to drive thermo- electric coolers (tecs) in space-constrained optical modules. both devices deliver ?.5a output current and control the tec current to eliminate harmful current surges. on-chip fets minimize external components and high switching frequency reduces the size of exter- nal components. the max8520/max8521 operate from a single supply and bias the tec between the outputs of two synchronous buck regulators. this operation allows for temperature control without ?ead zones?or other nonlinearities at low current. this arrangement ensures that the control system does not hunt when the set-point is very close to the natural operating point, requiring a small amount of heating or cooling. an analog control signal precisely sets the tec current. both devices feature accurate, individually-adjustable heating current limit and cooling current limit along with maximum tec voltage limit to improve the reliability of optical modules. an analog output signal monitors the tec current. a unique ripple cancellation scheme helps reduce noise. the max8520 is available in a 5mm x 5mm tqfn pack- age and its switching frequency is adjustable up to 1mhz through an external resistor. the max8521 is also available in a 5mm x 5mm tqfn as well as space-saving 3mm x 3mm ucsp and 36-bump wlp (3mm x 3mm) packages, with a pin-selectable switch- ing frequency of 500khz or 1mhz. applications sff/sfp modules fiber optic laser modules fiber optic network equipment ate biotech lab equipment features circuit footprint 0.31in 2 low profile design on-chip power mosfets high-efficiency switch-mode design ripple cancellation for low noise direct current control prevents tec current surges 5% accurate adjustable heating/cooling current limits 2% accurate tec voltage limit no dead zone or hunting at low output current itec monitors tec current 1% accurate voltage reference switching frequency up to 1mhz synchronization (max8521) max8520/max8521 smallest tec power drivers for optical modules ________________________________________________________________ maxim integrated products 1 ordering information 19-2586; rev 2; 2/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package max8520 etp+ -40 c to +85 c 20 tqfn - e p * 5m m x 5m m max8521 ebx -40 c to +85 c 6 x 6 u c s p 3m m x 3m m max8521etp+ -40 c to +85 c 20 tqfn - e p * 5m m x 5m m max8521ewx+ -40 c to +85 c 36 wlp ** 3m m x 3m m ucsp is a trademark of maxim integrated products, inc. input 3v to 5.5v v dd pvdd_ comp gnd shdn itec on off tec current monitor ctli lx1 pgnd1 cs os1 os2 lx2 pgnd2 tec i tec = 1.5a ref current- control signal freq analog /digital temperature control output max8521 typical operating circuit pin configurations appear at end of data sheet + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. ** four center bumps depopulated.
max8520/max8521 smallest tec power drivers for optical modules 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v shdn , maxv, maxip, maxin, ctli to gnd .........................................................-0.3v to +6v comp, freq, os1, os2, cs, ref, itec to gnd...........................................-0.3v to (v dd + 0.3v) pvdd1, pvdd2 to gnd .............................-0.3v to (v dd + 0.3v) pvdd1, pvdd2 to v dd ..........................................-0.3v to +0.3v pgnd1, pgnd2 to gnd .......................................-0.3v to +0.3v comp, ref, itec short to gnd....................................indefinite lx current (note 1) ........................................?.25a lx current continuous power dissipation (t a = +70?) 6 x 6 ucsp (derate 22mw/? above +70?) ...............1.75w 20-pin 5mm x 5mm x 0.9mm tqfn (derate 20.8mw/? above +70?) (note 2)...................................................1.67w 36-bump wlp (derate 22mw/? above +70?)............1.75w operating temperature range ...........................-40? to +85? maximum junction temperature .....................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) lead(pb)-free (tqfn, wlp)........................................+260? containing lead (ucsp)............................................. +240? electrical characteristics (v dd = v pvdd1 = v pvdd2 = v shdn = 5v, 1mhz mode (note 4). pgnd1 = pgnd2 = gnd, ctli = maxv = maxip = maxin = ref, t a = 0c to +85c , unless otherwise noted. typical values at t a = +25?.) parameter symbol conditions min typ max units input supply range v dd 3.0 5.5 v maximum tec current 1.5 a reference voltage v ref v dd = 3v to 5.5v, i ref = 150? 1.485 1.500 1.515 v reference load regulation ? v ref v dd = 3v to 5v, i ref = 10? to 1ma 1.2 5.0 mv v maxi_ = v ref 140 150 160 v dd = 5v v maxi_ = v ref /3 40 50 60 v maxi_ = v ref 143 150 155 maxip/maxin threshold accuracy v dd = 3v v maxi_ = v ref /3 45 50 55 mv v dd = 5v, i = 0.2a 0.09 0.14 nfet on-resistance r ds ( on-n ) v dd = 3v, i = 0.2a 0.11 0.16 ? v dd = 5v, i = 0.2a 0.14 0.23 pfet on-resistance r ds ( on-p ) v dd = 3v, i = 0.2a 0.17 0.30 ? v lx = v dd = 5v, t a = +25 c 0.03 4.00 nfet leakage i leak(n) v lx = v dd = 5v t a = +85 c 0.3 ? v lx = 0v, t a = +25 c 0.03 4.00 pfet leakage i leak(p) v lx = 0v, t a = +85 c 0.3 ? note 1: lx has internal clamp diodes to pgnd and pvdd. applications that forward bias these diodes should take care not to exceed the ic? package power dissipation limits. note 2: solders underside metal slug to pcb ground plane. package thermal characteristics (note 3) 20 tqfn junction-to-ambient thermal resistance ( ja )...............30?/w junction-to-case thermal resistance ( jc )......................2?/w 6x6 ucsp junction-to-ambient thermal resistance ( ja )................65.5?/w junction-to-case thermal resistance ( jc ).......................0?/w 36 wlp junction-to-ambient thermal resistance ( ja )..................38?/w junction-to-case thermal resistance ( jc )......................4?/w note 3: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial .
max8520/max8521 smallest tec power drivers for optical modules _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = v pvdd1 = v pvdd2 = v shdn = 5v, 1mhz mode (note 4). pgnd1 = pgnd2 = gnd, ctli = maxv = maxip = maxin = ref, t a = 0c to +85c , unless otherwise noted. typical values at t a = +25?.) parameter symbol conditions min typ max units 500khz mode 11 14 v comp = v ref = 1.500v, v dd = 5v 1mhz mode 16 21 500khz mode 8 11 no-load supply current i dd(no load) v comp = v ref = 1.500v, v dd = 3.3v 1mhz mode 11 14 ma shutdown supply current i dd-sd shdn = gnd, v dd = 5v, (note 5) 2 3 ma thermal shutdown t shutdown hysteresis = 15 c +165 c v dd rising 2.50 2.65 2.80 uvlo threshold v uvlo v dd falling 2.40 2.55 2.70 v max8521, freq = v dd , v dd = 3v to 5v 0.8 1.0 1.2 max8521, freq = gnd, v dd = 3v to 5v 0.4 0.5 0.6 max8520, r ext = 60k ? , v dd = 5v 0.8 1.0 1.2 max8520, r ext = 60k ? , v dd = 3v 0.76 0.93 1.10 max8520, r ext = 150k ? , v dd = 5v 0.4 0.5 0.6 internal oscillator switching frequency f sw-int max8520, r ext = 150k ? , v dd = 3v 0.36 0.46 0.56 mhz external sync frequency range 25% < duty cycle < 75% (max8521 only) 0.7 1.2 mhz lx_ duty cycle (note 6) 0 100 % os1, os2, cs input current i os1 , i os2 , i cs 0v or v dd -100 +100 ? shdn , freq input current i shdn , i freq 0v or v dd , freq applicable for the max8521 only -5 +5 ? shdn , freq input low voltage v il v dd = 3v to 5.5v, freq applicable for the max8521 only v dd x 0.25 v shdn , freq input high voltage v ih v dd = 3v to 5.5v, freq applicable for the max8521 only v dd x 0.75 v v maxv = v ref x 0.67, v os1 to v os2 = 4v, v dd = 5v -2 +2 % maxv threshold accuracy v maxv = v ref x 0.33, v os1 to v os2 = 2v, v dd = 3v -3 +3 % maxv, maxi_ input bias current i maxv-bias , i maxi_-bias v maxv = v maxi_ = 0.1v or 1.5v -0.1 +0.1 a ctli gain a ctli v ctli = 0.5v to 2.5v (note 7) 9.5 10.0 10.5 v/v ctli input resistance r ctli 1m ? terminated at ref 0.5 1.0 2.0 m ? error-amp transconductance g m 50 100 160 ? v itec accuracy v os1 to v cs = 100mv v os1 = v dd /2 -10 +10 %
max8520/max8521 smallest tec power drivers for optical modules 4 _______________________________________________________________________________________ electrical characteristics (v dd = v pv dd1 = v pv dd2 = v shdn = 5v, 1mhz mode (note 4). pgnd1 = pgnd2 = gnd, ctli = maxv = maxip = maxin = ref, t a = -40c to +85c , unless otherwise noted.) (note 8) parameter symbol conditions min max units input supply range v dd 3.0 5.5 v maximum tec current 1.5 a reference voltage v ref v dd = 3v to 5.5v, i ref = 150? 1.480 1.515 v reference load regulation ? v ref v dd = 3v to 5v, i ref = 10? to 1ma 5 mv v maxi_ = v ref 140 160 v dd = 5v v maxi_ = v ref /3 40 60 v maxi_ = v ref 143 155 maxip/maxin threshold accuracy v dd = 3v v maxi_ = v ref /3 45 55 mv v dd = 5v, i = 0.2a 0.14 nfet on-resistance r ds ( on-n ) v dd = 3v, i = 0.2a 0.16 ? v dd = 5v, i = 0.2a 0.23 pfet on-resistance r ds ( on-p ) v dd = 3v, i = 0.2a 0.30 ? 500khz mode 14 v comp = v ref = 1.500v, v dd = 5v 1mhz mode 21 500khz mode 11 no load supply current i dd(no load) v comp = v ref = 1.500v, v dd = 3.3v 1mhz mode 14 ma shutdown supply current i dd-sd shdn = gnd, v dd = 5v (note 5) 3 ma v dd rising 2.50 2.80 uvlo threshold v uvlo v dd falling 2.40 2.70 v max8521, freq = v dd , v dd = 3v to 5v 0.8 1.2 max8521, freq = gnd, v dd = 3v to 5v 0.4 0.6 max8520, r ext = 60k ? , v dd = 5v 0.8 1.2 max8520, r ext = 60k ? , v dd = 3v 0.76 1.10 max8520, r ext = 150k ? , v dd = 5v 0.4 0.6 internal oscillator switching frequency f sw-int max8520, r ext = 150k ? , v dd = 3v 0.36 0.56 mhz external sync frequency range 25% < duty cycle < 75% (max8521 only) 0.7 1.2 mhz lx_ duty cycle note 6 0 100 % os1, os2, cs input current i os1 , i os2 , i cs 0v or v dd -100 +100 ? shdn , freq input current i shdn , i freq 0v or v dd , freq applicable for the max8521 only -5 +5 ? shdn , freq input low voltage v il v dd = 3v to 5.5v, freq applicable for the max8521 only v dd x 0.25 v shdn , freq input high voltage v ih v dd = 3v to 5.5v, freq applicable for the max8521 only v dd x 0.75 v
max8520/max8521 smallest tec power drivers for optical modules _______________________________________________________________________________________ 5 electrical characteristics (continued) (v dd = v pv dd1 = v pv dd2 = v shdn = 5v, 1mhz mode (note 4). pgnd1 = pgnd2 = gnd, ctli = maxv = maxip = maxin = ref, t a = -40c to +85c , unless otherwise noted.) (note 8) parameter symbol conditions min max units v maxv = v ref x 0.67, v os1 to v os2 = 4v, v dd = 5v -2 +2 % maxv threshold accuracy v maxv = v ref x 0.33, v os1 to v os2 = 2v, v dd = 3v -3 +3 % maxv, maxi_ input bias current i maxv- bias , i maxi_-bias v maxv = v maxi_ = 0.1v or 1.5v -0.1 +0.1 a ctli gain a ctli v ctli = 0.5v to 2.5v (note 7) 9.5 10.5 v/v ctli input resistance r ctli 1m ? terminated at ref 0.5 2.0 m ? error-amp transconductance g m 50 160 ? v itec accuracy v os1 to v cs = 100mv v os1 = v dd /2 -10 +10 % note 4: enter 1mhz mode by connecting a 60k ? resistor from freq to ground for the max8520, and connecting freq to v dd for the max8521. note 5: includes power fet leakage. note 6: duty-cycle specification is guaranteed by design and not production tested. note 7: ctli gain is defined as: note 8: specifications to -40? are guaranteed by design and not production tested. a v vv ctli ctli os cs = ? () ? ? 1 typical operating characteristics (v dd = 5v, circuit of figure 1, t a = +25? unless otherwise noted.) efficiency vs. tec current v dd = 5v, r tec = 2 ? max8520/21 toc01 tec curent (a) efficiency (%) 1.4 1.2 0.8 1 0.4 0.6 0.2 10 20 30 40 50 60 70 80 90 0 0 1.6 freq = 500khz freq = 1mhz efficiency vs. tec current v dd = 3.3v, r tec = 1.3 ? max8520/21 toc02 tec current (a) efficiency (%) 1.4 1.2 0.8 1 0.4 0.6 0.2 10 20 30 40 50 60 70 80 90 0 01.6 freq = 500khz freq = 1mhz common-mode output voltage ripple max8520/21 toc03 400ns/div v os2 20mv/div ac-coupled v os1 20mv/div ac-coupled i tec = 1a c 2 = c 7 = 1 f
max8520/max8521 smallest tec power drivers for optical modules 6 _______________________________________________________________________________________ differential output voltage ripple max8520/21 toc04 400ns/div v os2 - v os1 1mv/div ac-coupled c 2 = c 7 = 1 f i tec = 1a v dd ripple max8520/21 toc05 400ns/div v dd 20mv/div ac-coupled i tec = 1a tec current ripple max8520/21 toc06 400ns/div 10ma/div ac-coupled 0a 1.5a tec current vs. ctli voltage max8520/21 toc07 20ms/div v ctli 1v/div i tec 1a/div 0a 0v zero-crossing tec current max8520/21 toc08 1ms/div v ctli i00mv/div i tec 100ma/div 0a 1.5v v itec vs. tec current max8520/21 toc09 tec current (a) v itec (v) 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 0.5 1.0 1.5 2.0 2.5 3.0 0 -2.0 2.0 typical operating characteristics (continued) (v dd = 5v, circuit of figure 1, t a = +25? unless otherwise noted.) i tec vs. ambient temperature max8520/21 toc10 ambient temperature ( c) tec current (a) +60 +40 +20 0 -20 0.460 0.470 0.480 0.490 0.500 0.510 0.520 0.450 -40 +80 freq = 1mhz v ctli = 2v r tec = 1 ? switching frequency vs. temperature max8520/21 toc11 temperature ( c) switching frequency (khz) +80 +60 +40 +20 0 -20 500 600 700 800 900 1000 1100 400 -40 freq = 1mhz v ctli = 1.5v r tec = 1 ? freq = 500khz
max8520/max8521 smallest tec power drivers for optical modules _______________________________________________________________________________________ 7 switching frequency change vs. v dd max8520/21 toc12 v dd (v) switching frequency change (khz) 5.0 4.5 4.0 3.5 200 400 600 800 1000 1200 0 3.0 5.5 freq = 500khz freq = 1mhz switching frequency vs. r ext max8520/21 toc13 r ext (k ? ) switching frequency (khz) 140 120 100 80 500 600 700 800 900 1000 1100 400 60 160 v dd = 3.3v v dd = 5v v dd step response max8520/21 toc19 10ms/div v dd 2v/div i tec 10ma/div 1a 0v reference voltage change vs. v dd max8520/21 toc14 v dd (v) reference voltage change (mv) 5.0 4.5 4.0 3.5 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 -1.4 3.0 5.5 ref sourcing 150 a reference voltage change vs. temperature max8520/21 toc15 temperature ( c) reference voltage change (mv) +80 +40 +60 0 +20 -20 -4 -3 -2 -1 0 1 2 3 4 5 -5 -40 ref sourcing 150 a reference voltage change vs. load current max8520/21 toc16 load current (ma) reference voltage change (mv) 0.8 0.6 0.4 0.2 -10 -8 -6 -4 -2 0 -12 01.0 startup and shutdown waveforms max8520/21 toc17 200 s/div v shdn 5v/div i tec 500ma/div i dd 200ma/div 0ma 0ma 0v ctli step response max8520/21 toc18 1ms v ctli 1v/div i tec 1a/div 0a 1.5v typical operating characteristics (continued) (v dd = 5v, circuit of figure 1, t a = +25? unless otherwise noted.)
max8520/max8521 smallest tec power drivers for optical modules 8 _______________________________________________________________________________________ typical operating characteristics (continued) (v dd = 5v, circuit of figure 1, t a = +25? unless otherwise noted.) thermal stability, cooling mode max8520/21 toc20 4s/div temperature 0.001 c/div t tec = +25 c t a = +45 c thermal stability, room temperature max8520/21 toc21 4s/div temperature 0.001 c/div t tec = +25 c t a = +25 c thermal stability, heating mode max8520/21 toc22 4s/div temperature 0.001 c/div t tec = +25 c t a = +5 c pin description pin tqfn ucsp/wlp name function 1 e1, e2 lx1 inductor connection. lx1 is high-impedance in shutdown. 2 d1, d2, d3 pgnd1 power ground 1. internal synchronous-rectifier ground connection. connect all pgnd pins together at power ground plane. 3c1 shdn shutdown control input. pull shdn low to turn off pwm control and itec output. 4 c2 comp current-control loop compensation. see the compensation capacitor section. 5 b1 itec tec current-monitor output. the itec output voltage is a function of the voltage across the tec current-sense resistor. v itec = v ref + 8 (v os - v cs ). keep capacitance on itec < 150pf. 6 a1 maxin maximum negative tec current. connect maxin to ref to set default negative current limit to - 150mv/r sense . to lower this current limit, connect maxin to a resistor-divider network from ref to gnd. the current limit will then be equal to -(v maxin /v ref ) x (150mv/r sense ). 7 a2 maxip maximum positive tec current. connect maxip to ref to set default positive current limit to 150mv/r sense . to lower this current limit, connect maxip to a resistor-divider network from ref to gnd. the current limit will then be equal to (v maxip /v ref ) x (150mv/r sense ). 8 a3 maxv maximum bipolar tec voltage. connect maxv to ref to set default maximum tec voltage to v dd . to lower this limit, connect maxv to a resistor-divider network from ref to gnd. the maximum tec voltage is equal to 4 x v maxv or v dd , whichever is lower. 9 a4 ref 1.50v reference output. bypass ref to gnd with a 0.1? ceramic capacitor.
max8520/max8521 smallest tec power drivers for optical modules _______________________________________________________________________________________ 9 pin tqfn ucsp/wlp name function 10 a5 ctli tec current-control input. sets tec current. center point is 1.50v (no tec current). the current is given by: i tec = (v os1 - v cs ) / r sense = (v ctli - 1.50) / (10 x r sense ). when (v ctli - v ref ) > 0v then v os2 > v os1 > v cs . 11 a6 gnd analog ground. star connect to pgnd at underside exposed pad for tqfn package. 12 b6 v dd analog supply voltage input. bypass v dd to gnd with a 1? ceramic capacitor. for max8520: analog freq set pin (see the switching frequency section). 13 c5 freq for max8521: digital freq selection pin. connect to v dd for 1mhz operation, connect to gnd for 500khz operation. the pwm oscillator can synchronize to freq by switching at freq between 700khz and 1.2mhz. 14 d6, d5, d4 pgnd2 power ground 2. internal synchronous rectifier ground connection. connect all pgnd pins together at the power ground plane. 15 e5, e6 lx2 inductor connection. lx2 is high-impedance in shutdown. 16 f5, f6 pvdd2 power input 2. connect all pvdd inputs together at the v dd power plane. 17 f4 cs current-sense input. the current through the tec is monitored between cs and os1. the maximum tec current is given by 150mv/r sense and is bipolar. 18 c6 os2 output sense 2. os2 senses one side of the differential tec voltage. os2 is a sense point, not a power output. os2 discharges to ground in shutdown. 19 f3 os1 output sense 1. os1 senses one side of the differential tec voltage. os1 is a sense point, not a power output. os1 discharges to ground in shutdown. 20 f1, f2 pvdd1 power input 1. connect all pvdd inputs together at the v dd power plane. b2, b5, c3, c4 gnd2 ground. additional ground pads aid in heat dissipation. short to either gnd or pgnd plane. b3, b4 e3, e4 n.c. no connect. connect n.c. pads to gnd2 to aid in heat dissipation. ep exposed paddle (tqfn only). internally connected to gnd. connect to a large ground plane to maximize thermal performance. not intended as an electrical connection point. pin description (continued)
max8520/max8521 smallest tec power drivers for optical modules 10 ______________________________________________________________________________________ detailed description the max8520/max8521 tec drivers consist of two switching buck regulators that operate together to directly control the tec current. this configuration cre- ates a differential voltage across the tec, allowing bi- directional tec current for controlled cooling and heating. controlled cooling and heating allow accurate tec temperature control to within 0.01?. the voltage at ctli directly sets the tec current. an external thermal- control loop is typically used to drive ctli. figures 1 and 2 show examples of the thermal-control-loop circuit. ripple cancellation switching regulators like those used in the max8520/ max8521 inherently create ripple voltage on the output. the dual regulators in the max8520/max8521 switch in-phase and provide complementary in-phase duty cycles so ripple waveforms at the tec are greatly reduced. this feature suppresses ripple currents and electrical noise at the tec to prevent interference with the laser diode. switching frequency for the max8521, freq sets the switching frequency of the internal oscillator. with freq = gnd, the oscilla- tor frequency is set to 500khz. the oscillator frequency is 1mhz when freq = v dd . for the max8520, connect a resistor (r ext in figure 2) from freq to gnd. choose r ext = 60k ? for 1mhz operation, and r ext = 150k ? for 500khz operation. for any intermediary frequency between 500khz and 1mhz, use the following equation to find the value of r ext value needed for v dd = 5v: where r ext is the resistance given in k ? , and fs is the desired frequency given in mhz. note that for v dd < 5v, the frequency is reduced slightly, to the extent of about 7% when v dd reaches 3v. this should be taken into consideration when selecting the value for r ext at known supply voltage. voltage and current-limit setting both the max8520 and max8521 provide control of the maximum differential tec voltage. applying a voltage to maxv limits the maximum voltage across the tec. the voltage at maxip and maxin sets the maximum positive and negative current through the tec. these current limits can be independently controlled. current monitor output itec provides a voltage output proportional to the tec current (i tec ). see the functional diagram for more detail: v itec = 1.5v +(8 (vos1-vcs)) reference output the max8520/max8521 include an on-chip voltage ref- erence. the 1.50v reference is accurate to 1% over temperature. bypass ref with 0.1? to gnd. ref can be used to bias an external thermistor for temperature sensing as shown in figures 1 and 2. thermal and fault-current protection the max8520/max8521 provide fault-current protec- tion in either fets by turning off both high-side and low-side fets when the peak current exceeds 3a in either fets. in addition, thermal-overload protection limits the total power dissipation in the chip. when the device? die junction temperature exceeds +165?, an on-chip thermal sensor shuts down the device. the thermal sensor turns the device on again after the junc- tion temperature cools down by +15?. design procedures duty-cycle range selection by design, the max8520/max8521 are capable of operating from 0% to 100% duty cycle, allowing both lx outputs to enter dropout. however, as the lx pulse width narrows, accurate duty-cycle control becomes difficult. this can result in a low-frequency noise appearing at the tec output (typically in the 20khz to 50khz range). while this noise is typically filtered out by the low thermal-loop bandwidth, for best result, operate the pwm with a pulse width greater than 200ns. for 500khz application, the recommended duty-cycle range is from 10% to 90%. for 1mhz application, it is from 20% to 80%. r fs ext = ? ? ? ? ? ? ? 90 11 3 tec connection thermistor heating mode ptc cooling mode ntc table 1. tec connection for figure 1 tec connection thermistor heating mode ntc cooling mode ptc table 2. tec connection for figure 2
max8520/max8521 smallest tec power drivers for optical modules ______________________________________________________________________________________ 11 v dd r sense 0.09 ? c2 1 f c5 10 f l2 4.7 f r2 ref r ther lx1 v dd l1 4.7 f cs os1 os2 pvdd1 c1 1 f c3 1 f c4 1 f c6 0.1 f 49.9k ? 100k ? pgnd1 pgnd2 ref maxip maxin maxv pvdd2 max8521 lx2 comp freq itec on off shdn ctli gnd 0.022 f 10 f 243k ? 10k ? 1 f 510k ? 100k ? 10k ? to ref dac inputs v dd v dd c7 1 f c8 0.1 f max4477 max4477 max4475 max5144 u1 u2 u4 u3a u3b figure 1. max8521 typical application circuit
max8520/max8521 smallest tec power drivers for optical modules 12 ______________________________________________________________________________________ v dd r sense 0.09 ? c2 1 f c5 10 f l2 4.7 f r2 ref lx1 v dd l1 4.7 f cs os1 os2 pvdd1 c1 1 f c3 1 f c4 1 f c6 0.1 f 49.9k ? 100k ? pgnd1 pgnd2 ref maxip maxin maxv pvdd2 max8520 lx2 comp freq itec on off shdn ctli gnd 0.022 f 10 f 243k ? 1k ? 10 f 50k ? 0.01 f ref dac inputs v dd c7 1 f c8 0.1 f r ext 60k ? r ther max5144 u1 max4238 u2 u4 figure 2. typical application circuit for the max8520 with reduced op-amp count configuration
max8520/max8521 smallest tec power drivers for optical modules ______________________________________________________________________________________ 13 inductor selection the max8520/max8521 dual buck converters operate in-phase and in complementary mode to drive the tec differentially in a current-mode control scheme. at zero tec current, the differential voltage is zero, hence the outputs with respect to gnd are equal to half of v dd . as the tec current demand increases, one output will go up and the other will go down from the initial point of 0.5v dd by an amount equal to 0.5 v tec (v tec = i tec r tec ). therefore, the operating duty cycle of each buck converter depends on the operating i tec and r tec . since inductor current calculation for heating and cooling are identical, but reverse in polarity, the calcu- lation only needs to be carried out for either one. for a given inductor, and input voltage, the maximum inductor ripple current happens when the duty cycle is at 50%. therefore, the inductor should be calculated at 50% duty cycle to find the maximum ripple current. the maximum desired ripple current of a typical standard buck converter is in the range of 20% to 40% of the maximum load. the higher the value of the inductor, the lower the ripple current. however, the size will be phys- ically larger. for the tec driver the thermal loop is inherently slow, so the inductor can be larger for lower ripple current for better noise and emi performance. picking an inductor to yield ripple current of 10% to 20% of the maximum tec current is a good starting point. calculate the inductor value as follows: where lir is the selected inductor ripple-current ratio, i tec(max) is the maximum tec current, and fs is the switching frequency as an example, for v dd = 3.3v, lir = 12%, and fs = 1mhz, l = 4.58? even though each inductor ripple current is at its maxi- mum at 50% duty cycle (zero tec current), the ripple cancels differentially because each is equal and in- phase. output filter capacitor selection common-mode filter capacitors the common-mode filter capacitors (c2 and c7 of figure 1) are used as filter capacitors to ground for each output. the output ripple voltage depends on the capacitance, the esr of these capacitors, and the inductor ripple current. ceramic capacitors are recom- mended for their low esr and impedance at high fre- quency. l v lir i fs dd tec max = () 025 . () ctli r sense cs os1 c comp r r 0.5x ref 1.2x comp pwm 4x lx2 3/4 v dd 1/4 v dd lx1 -1.2 +1.2 10x 1 gm figure 3. functional diagram of the current-control loop
max8520/max8521 the output common-mode ripple voltage can be calcu- lated as follows: v ripplepk-pk = lir x i tec(max) (esr + 1/8 x c x fs) a 1? ceramic capacitor with esr of 10 m ? with lir = 12% and i tec(max) = 1.5a will result in v ripple(p-p) of 24.3mv. for size-constraint application, the capacitor can be made smaller at the expense of higher ripple voltage. however, the capacitance must be high enough so that the lc resonant frequency is less than 1/5 the switching frequency: where f is the resonant frequency of the output filter. differential mode filter capacitor the differential-mode filter capacitor (c5 in figure 1) is used to bypass differential ripple current through the tec as the result of unequal duty cycle of each output. this happens when the tec current is not at zero. as tec current increases from zero, both outputs move away from the 50% duty-cycle point complementarily. the common-mode ripple decreases, but the differential ripple does not cancel perfectly, and there will be a resulting differential ripple. the maximum value happens when one output is at 75% duty cycle and the other is at 25% duty cycle. at this operating point, the differential ripple is equal to 1/2 of the maximum common-mode rip- ple. the tec ripple current determines the tec perfor- mance, because the maximum temperature differential that can be created between the terminals of the tec depends on the ratio of ripple current and dc current. the lower the ripple current, the closer to the ideal maxi- mum. the differential-mode capacitor provides a low- impedance path for the ripple current to flow, so that the tec ripple current is greatly reduced. the tec ripple current then can be calculated as follows: i tec(ripple) = (0.5 x lir x i tec(max) ) x (z c5 )/(r tec + r sense + z c5 ) where z c5 is the impedance of c5 at twice the switching frequency, r tec is the tec equivalent resistance, and r sense is the current-sense resistor. decoupling capacitor selection decouple each power supply input (v dd , pvdd1, pvdd2) with a 1? ceramic capacitor close to the sup- ply pins. in applications with long distances between the source supply and the max8520/max8521, addi- tional bypassing may be needed to stabilize the input supply. in such cases, a low-esr electrolytic or ceramic capacitor of 100? or more at v dd is sufficient. compensation capacitor a compensation capacitor is needed to ensure current- control-loop stability (see figure 3). select the capacitor so that the unity-gain bandwidth of the current-control loop is less than or equal to 10% the resonant frequency of the output filter: where: f bw = unity-gain bandwidth frequency, less than or equal to 10% the output filter resonant frequency g m = loop transconductance, typically 100?/v c comp = value of the compensation capacitor r tec = tec series resistance, use the minimum resis- tance value r sense = sense resistor setting voltage and current limits certain tec parameters must be considered to guarantee a robust design. these include maximum positive current, maximum negative current, and the maximum voltage allowed across the tec. these limits should be used to set the maxip, maxin, and maxv voltages. setting max positive and negative tec current maxip and maxin set the maximum positive and nega- tive tec currents, respectively. the default current limit is ?50mv/r sense when maxip and maxin are con- nected to ref. to set maximum limits other than the defaults, connect a resistor-divider from ref to gnd to set v maxi_ . use resistors in the 10k ? to 100k ? range. v maxi_ is related to itec by the following equations: v maxip = 10(i tecp(max) r sense ) v maxin = 10(i tecn(max) r sense ) where i tecp(max) is the maximum positive tec current and i tecn(max) is the negative maximum tec current. positive tec current occurs when cs is less than os1: i tec x r sense = os1 - cs when i tec > 0a. i tec r sense = cs - os1 when i tec < 0a. c g f r rr comp m bw sense sense tec ? ? ? ? ? ? ? ? ? ? ? ? 24 2 () f lc = 1 2 smallest tec power drivers for optical modules 14 ______________________________________________________________________________________
take care not to exceed the positive or negative cur- rent limit on the tec. refer to the manufacturer? data sheet for these limits. setting max tec voltage apply a voltage to the maxv pin to control the maxi- mum differential tec voltage. v maxv can vary from 0v to v ref . the voltage across the tec is four times v maxv and can be positive or negative: |v os1 - v os2 | = 4 x v maxv or v dd , whichever is lower set v maxv with a resistor-divider between ref and gnd using resistors from 10k ? to 100k ? . v maxv can vary from 0v to v ref . control inputs/outputs output current control the voltage at ctli directly sets the tec current. ctli is typically driven from the output of a temperature con- trol loop. the transfer function relating current through the tec (i tec ) and v ctli is given by: i tec = (v ctli - v ref )/(10 r sense ) where v ref is 1.50v and: itec = (v os1 - v cs )/r sense ctli is centered around ref (1.50v). i tec is zero when ctli = 1.50v. when v ctli > 1.50v the current flow is from os2 to os1. the voltages on the pins relate as follows: v os2 > v os1 > v cs the opposite applies when v ctli < 1.50v current flows from os1 to os2: v os2 < v os1 < v cs shutdown control the max8520/max8521 can be placed in a power-saving shutdown mode by driving shdn low. when the max8520/max8521 are shut down, the tec is off (os1 and os2 decay to gnd) and supply current is reduced to 2ma (typ). itec output itec is a status output that provides a voltage proportional to the actual tec current. v itec = v ref when tec current is zero. the transfer function for the itec output is: v itec = 1.50v + 8 (v os1 ?v cs ) use itec to monitor the cooling or heating current through the tec. for stability keep the load capaci- tance on itec to less than 150pf. applications information the max8520/max8521 typically drive a thermo-elec- tric cooler inside a thermal-control loop. tec drive polarity and power are regulated based on temperature information read from a thermistor or other temperature- measuring device to maintain a stable control tempera- ture. temperature stability of +0.01? can be achieved with carefully selected external components. there are numerous ways to implement the thermal loop. figures 1 and 2 show designs that employ precision op amps, along with a dac or potentiometer to set the con- trol temperature. the loop can also be implemented digi- tally, using a precision a/d to read the thermistor or other temperature sensor, a microcontroller to implement the control algorithm, and a dac (or filtered-pwm signal) to send the appropriate signal to the max8520/max8521 ctli input. regardless of the form taken by the thermal- control circuitry, all designs are similar in that they read temperature, compare it to a set-point signal, and then send an error-correcting signal to the max8520/ max8521 that moves the temperature in the appropriate direction. pcb layout and routing high switching frequencies and large peak currents make pcb layout a very important part of design. good design minimizes excessive emi and voltage gradients in the ground plane, both of which can result in instabil- ity or regulation errors. follow these guidelines for good pcb layout: 1) place decoupling capacitors as close to the ic pins as possible. 2) keep a separate power ground plane, which is con- nected to pgnd1 and pgnd2. pvdd1, pvdd2, pgnd1 and pgnd2 are noisy points. connect decou- pling capacitors from pvdd_ to pgnd_ as direct as possible. output capacitors c2, c7 returns are con- nected to pgnd plane. 3) connect a decoupling capacitor from v dd to gnd. connect gnd to a signal ground plane (separate from the power ground plane above). other v dd decoupling capacitors (such as the input capacitor) need to be connected to the pgnd plane. 4) connect gnd and pgnd_ pins together at a single point, as close as possible to the chip. 5) keep the power loop, which consists of input capaci- tors, output inductors and capacitors, as compact and small as possible. max8520/max8521 smallest tec power drivers for optical modules ______________________________________________________________________________________ 15
max8520/max8521 6) to ensure high dc-loop gain and minimum loop error, keep the board layout adjacent to the negative input pin of the integrator (u2 in figure1) clean and free of moisture. any contamination or leakage current into this node can act to lower the dc gain of the integrator which can degrade the accuracy of the thermal loop. if space is available, it can also be helpful to surround the negative input node of the integrator with a grounded guard ring. refer to the max8520/max8521 evaluation kit for a pcb layout example. chip information process: bicmos smallest tec power drivers for optical modules 16 ______________________________________________________________________________________ 20 19 18 17 pvdd1 os1 os2 cs 16 pvdd2 13 12 11 14 15 v dd freq pgnd2 lx2 gnd 4 3 2 1 comp shdn pgnd1 lx1 5 itec 6 7 8 9 maxim maxip maxv ref 10 ctli max8520/ max8521 top view connect ep to gnd tqfn + ep f6 pvdd2 lx2 lx2 lx1 lx1 pgnd2 pgnd2 pgnd2 pgnd1 pgnd1 pgnd1 os2 freq gnd2 gnd2 comp shdn vdd gnd2 gnd2 itec gnd ctli ref maxv max8521 maxip maxin pvdd2 cs os1 pvdd1 pvdd1 f5 f4 f3 f2 f1 e6 e5 e2 e1 d6 d5 d4 d3 d2 d1 c6 c5 c4 c3 c2 c1 b6 b5 b2 b1 a6 a5 a4 a3 a2 a1 + ucsp/wlp top view bumps on bottom pin configurations package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per - tains to the package regardless of rohs status. package type package code outline no. land pattern no. 20 tqfn-ep t2055+4 21-0140 90-0009 6 x 6 ucsp b36-2 21-0082 refer to application note 1891 36 wlp w363a3+2 21-0024 refer to application note 1891
max8520/max8521 smallest tec power drivers for optical modules ______________________________________________________________________________________ 17 gnd freq (max8520) comp ctli itec maxip freq (max8521) pwm control and gate control maxin r sense pgnd1 pgnd2 maxv ref shdn ref os1 os2 cs lx1 lx2 on off 3v to 5.5v os1 ref cs max v tec = v maxv 4 or v dd max i tec = (v maxip /v ref ) (0.15v/r sense ) max i tec = (v maxin /v ref ) (0.15v/r sense ) pvdd1 pvdd2 v dd v dd max8521/ max8520 functional diagram
max8520/max8521 smallest tec power drivers for optical modules maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 10/02 initial release 1 12/08 added wlp package to ordering information , updated electrical characteristics , absolute maximum ratings , pin description , and package information . 1?, 8, 9, 15?8 2 2/11 update absolute maximum ratings , add wlp to pin description , update style 1?, 8, 9, 11, 14?8

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